library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.numeric_bit.all;
    
entity DRMUX_logic is
    port(IR_out: in unsigned(15 downto 0);
         DRMUX: in bit_vector(1 downto 0);
         DRMUX_out: out unsigned(3 downto 0));
     end entity DRMUX_logic;

architecture build of DRMUX_logic is
    begin
        process(DRMUX,IR_out)
            begin
                if DRMUX = "00" then
                    DRMUX_out <= IR_out(11 downto 8);
                elsif DRMUX = "01" then
                    DRMUX_out <= "1110";
                else
                    DRMUX_out <= "1111";
                end if;
            end process;
    end build;
